FIG. 1 illustrates a prior art memory interface 100. An arbiter 105 receives memory access requests from a plurality of clients 110-A, 110-B, and 110-C. The arbiter 105 arbitrates memory access requests from the different clients and places a sequence of commands into command queue 115 to service each client. Command queue 115 is typically implemented as a first in, first out (FIFO) such that the commands progress in order through the FIFO. A dynamic random access memory (DRAM) controller 120 issues commands to a DRAM memory (not shown in FIG. 1. As illustrated in FIG. 2, a DRAM memory may include a memory module 200 having a set of memory banks with a common interface. An activate command is used to activate a tow in a bank and thus typically specifies a bank number and a row address. Data is then either read or written. Data is typically read or written as chunks of data over multiple clock cycles. Additionally, a read or a write also includes a bank number and a column address given to a memory chip. A row in a particular bank is open until it is closed with a precharge command. There are well-known time delays associated with performing a precharge
Conventionally, arbiter 10S may attempt to place commands for the different clients in command queue 115 into a sequence of commands selected to achieve interleaving. For example, if the commands have an order in command queue 115 of 0, 1, and 2 then command queue 115 may have pointers to initiate precharge, activate and read/write (R/W) operations with memory banks accessed via DRAM controller 120 in the same order as the command queue. This permits, for example, memory commands entering the command queue to get an early start on preparing the memory banks for reads/writes taken out later at the queue head. For example a read/write can be performed for command “0” at the queue head, an activate for command “1”, and a precharge for command “2.” To support interleaving special “bank in use” tracking hardware 107 is typically included for arbiter 105 to keep track of the arbitration history.
One problem with the prior art is that the serial nature of a FIFO command queue 115 can make it difficult for arbiter 105 to select an ideal interleaving that avoids bank conflicts and does not waste clock cycles. Moreover, some commands may take a long access time while other commands may have an access time that is variable. As a consequence, in some applications it is difficult for arbiter 105 to make arbitration decisions that efficiently utilize the DRAM memory, resulting in lost clock cycles in which no productive work is performed.
Another problem with the prior art is latency introduced by command queue 115. The intent is to introduce enough delay between the precharge, activate, and read/write commands to facilitate overlapping bank operations. Too much delay adds undesired latency to requests. As one example, memory interface 100 may include a compression module 130 to perform read-modify-writes on atomic units of memory (e.g., memory tiles) based on whether a tag indicates that the source data is compressed or uncompressed. Some types of write commands may require decompression, resulting in a greater number of clock cycles to perform a full memory access operation. For example, a read-modify-write may include reading compressed data, decompressing the data, and writing the data back to memory to permit a client to perform a write. However, if the data is uncompressed, then a simple write operation is performed instead, which is a much shorter operation. As a result, there is potential variability in the time required to complete a memory access request. If several of these requests were residing in the command queue, latency would be unnecessarily high.
In light of the above-described problems, the apparatus and method of the present invention was developed.